Proven Technology for an Array of Embedded Applications. Read more. Browse by Compatibility. Find Direct Replacements. Find Non-Direct Replacements. Browse by Core Application. Single-Cycle Core. See Devices. Lighting MCUs. Privacy Policy. Stay on the leading edge with our blog. This website uses cookies for analytics, personalization, and other purposes. Click to learn more. Explore Magazines. Editors' Picks All magazines. Explore Podcasts All podcasts. Difficulty Beginner Intermediate Advanced.
Explore Documents. Uploaded by Narasimman Don. Document Information click to expand document information Description: workshop. Original Title ppt. Did you find this document useful? Is this content inappropriate? Report this Document. Description: workshop. Flag for inappropriate content. Download now. Save Save ppt For Later. Original Title: ppt. Related titles. Carousel Previous Carousel Next. Jump to Page. Search inside document. Conti If you use a frequency source other than a crystal oscillator, such as a TTL oscillator 1.
It will be connected to XTAL1 2. Documents Similar To ppt. DDragos George. Vinay Kr. In the latter case, the PC is incremented to the address of the following instruction before being added with the Accumulator; otherwise the base register is not altered. Sixteen-bit addition is performed so a carry-out from the low-order eight bits may propagate through higher-order bits.
Example: A value between 0 and 3 is in the Accumulator. The following instructions will translate the value in the Accumulator to one of four values defined by the DB define byte directive. If several bytes of code separate the MOVC from the table, the corresponding number is added to the Accumulator instead. There are two types of instructions, differing in whether they provide an 8-bit or bit indirect address to the external data RAM.
In the first type, the contents of R0 or R1 in the current register bank provide an 8-bit address multiplexed with data on P0. For somewhat larger arrays, any output port pins can be used to output higher-order address bits.
These pins are controlled by an output instruction preceding the MOVX. This form of MOVX is faster and more efficient when accessing very large data arrays up to 64K bytes , since no additional instructions are needed to set up the output ports. It is possible to use both MOVX types in some situations. Port 3 provides control lines for the external RAM.
Registers 0 and 1 contain 12H and 34H. The low-order byte of the bit product is left in the Accumulator, and the high-order byte in B. If the product is greater than 0FFH , the overflow flag is set; otherwise it is cleared. The carry flag is always cleared. Example: Originally the Accumulator holds the value 80 50H. Register B holds the value 0A0H. The overflow flag is set, carry is cleared. Other than the PC, no registers or flags are affected.
Example: A low-going output pulse on bit 7 of Port 2 must last exactly 5 cycles. This may be done assuming no interrupts are enabled with the following instruction sequence, CLR P2. Note: When this instruction is used to modify an output port, the value used as the original port data is read from the output data latch, not the input pins.
When the destination is a directly addressed byte, the instruction can set combinations of bits in any RAM location or hardware register. The pattern of bits to be set is determined by a mask byte, which may be either a constant data value in the instruction or a variable computed in the Accumulator at run-time. Example: Set the carry flag if and only if P1.
The value read is then transferred to the directly addressed byte indicated. In this special case, the Stack Pointer was decremented to 2FH before being loaded with the value popped 20H. The contents of the indicated variable is then copied into the internal RAM location addressed by the Stack Pointer.
Otherwise no flags are affected. Example: On entering an interrupt routine, the Stack Pointer contains 09H. The Data Pointer holds the value H. Program execution continues at location H. The Stack Pointer is left decremented by two. No other registers are affected; the PSW is not automatically restored to its pre-interrupt status.
Program execution continues at the resulting address, which is generally the instruction immediately after the point at which the interrupt request was detected.
If a lower- or same-level interrupt was pending when the RETI instruction is executed, that one instruction is executed before the pending interrupt is processed. An interrupt was detected during the instruction ending at location H. Bit 7 is rotated into the bit 0 position. Bit 7 moves into the carry flag; the original state of the carry flag moves into the bit 0 position.
Bit 0 is rotated into the bit 7 position. Bit 0 moves into the carry flag; the original value of the carry flag moves into the bit 7 position. SETB can operate on the carry flag or any directly addressable bit. Output Port 1 has been written with the value 34H B.
The branch destination is computed by adding the signed displacement in the second instruction byte to the PC, after incrementing the PC twice. Therefore, the range of destinations allowed is from bytes preceding this instruction bytes following it.
After the instruction is executed, the PC contains the value H. Bytes: 2 Cycles: 2 Encoding: 1 0 0 0 0 0 0 0 rel. SUBB sets the carry borrow flag if a borrow is needed for bit 7 and clears C otherwise. If C was set before executing a SUBB instruction, this indicates that a borrow was needed for the previous step in a multiple-precision subtraction, so the carry is subtracted from the Accumulator along with the source operand.
AC is set if a borrow is needed for bit 3 and cleared otherwise. OV is set if a borrow is needed into bit 6, but not into bit 7, or into bit 7, but not bit 6. When subtracting signed integers, OV indicates a negative number produced when a negative value is subtracted from a positive value, or a positive result when a positive number is subtracted from a negative number.
The source operand allows four addressing modes: register, direct, register-indirect, or immediate. Notice that 0C9H minus 54H is 75H. The difference between this and the above result is due to the carry borrow flag being set before the operation. If the state of the carry is not known before starting a single or multiple-precision subtraction, it should be explicitly cleared by CLR C instruction.
The operation can also be thought of as a 4-bit rotate instruction. Example: R0 contains the address 20H. The Accumulator holds the value 3FH lB. The high-order nibbles bits of each register are not affected. The Accumulator holds the value 36H B. When the destination is a directly addressed byte, this instruction can complement combinations of bits in any RAM location or hardware register. The pattern of bits to be complemented is then determined by a mask byte, either a constant contained in the instruction or a variable computed in the Accumulator at run-time.
Correcto to MOV Direct, page No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice.
Atmel does not make any commitment to update the information contained herein. Unless specifically providedot- herwise, Atmel products are not suitable for, and shall not be used in, automotive applications.
All rights reserved. Copied by permission of Intel Corporation. Copyright Intel Corporation
0コメント